1. Field of the Invention
This invention relates generally to buffer controllers used in integrated circuits on-board a hard disk drive and more specifically to a page mode buffer controller that controls transfer of data to and from a buffer memory in read and write operations to the disk drive.
2. Description of Related Art
Many different devices have been used to interconnect a hard disk drive to the data bus of a computer system. One of the basic problems in such an interface is that data from the disk drive read/write head is serial data while the computer data bus is typically a parallel data bus. Further, the speed of the computer data bus is significantly different from the characteristic speed of the serial data from the read/write head.
To address these problems a variety of solutions have been used. One solution is to include an integrated circuit on board the disk drive that converts the serial data to parallel data. The parallel data is then supplied to a host interface circuit that supplies the parallel data to the computer data bus.
Typically, the integrated circuit on the disk drive includes a first-in-first-out (FIFO) memory that receives data from the disk. When the FIFO memory is full or nearly full, the data in the FIFO memory is transferred using a buffer controller to a buffer memory. The speed at which data is transferred from the disk to the buffer memory limits the performance of disk drive.
One of the limiting factors in the transfer of data to and from a disk is the buffer bandwidth. The buffer bandwidth is the rate, usually expressed in Megabytes per second (MB/s), that data may be transferred into and out of the buffer memory. This rate is a function of the number of bytes transferred to buffer memory between other operations that must be performed by the buffer memory controller.
Typically, the buffer memory is dynamic random access memory (DRAM) and the DRAM must be periodically refreshed. Also, the transfer of data is typically impeded by error correction operations, host transfer operations, and disk transfer operations. Error correction is used to determine that the data retrieved from the disk is the same as the data stored on the disk. Host transfer operations are actions initiated in the transfer of data between the buffer memory and the host computer. Disk transfer operations are actions to initiate transfer of data between the buffer memory and the disk.
Typically, prior art buffer memory controllers transferred four bytes in every data transfer to and from the buffer memory. FIG. 1 is a timing diagram for the prior art four byte data transfer to buffer memory. Signal "GO" is set active to initiate the four byte data transfer in state 0. On the next clock cycle in state 1, a state machine drives the row address strobe signal RAS-active(low). In state 3, the buffer address is incremented. On the fourth clock cycle in state 2, the column address strobe signal CAS- is set active (low). The actions in states 3 and 2 are repeated three times. In state 6, row address strobe signal RAS- is reset and in state 4, column address strobe CAS- is reset. Hence, the transfer of each data byte requires two clock cycles and there are four overhead clock cycles used to start and stop the four byte transfer. Consequently, twelve clock cycles are required to transfer the four bytes of data.
The transfer of four bytes limits the instantaneous buffer bandwidth to: EQU ( (4 Bytes) / (12 Clock cycles) )*(1 Clock Cycle/(TB seconds) ) =FB/3 MBytes/second
where EQU FB=1/TB
and
TB=the period for one buffer clock cycle.
Thus, for a 40 MHz buffer clock, the instantaneous buffer bandwidth is 13.333 MBytes/second. The only way to enhance the bandwidth for the fixed four byte data transfer is to go a higher frequency clock. However, as clock speed increases, power consumption of CMOS circuits increases. Further, most systems have clock frequencies of 50 MHz or less. However, the clock speeds that may be used are limited by DRAM technology. Thus, the fixed four byte buffer memory data transfer limits the overall performance of the disk drive.